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g56054-0, rev 1.0 sonet/sdh 2.5gbps transport terminating transceiver VSC9142 . 1.0 product description page 1 . 1.0 product description 1.1 functional overview

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g56054, rev 1.0 sts-48c physical layer packet/atm over sonet/sdh device VSC9142 page 2 1.0 product description . section generation tsop section trace buffer sstb intb rstb rdb wrb csb ale a[8..0] d[7..0] lof los rxrclk phy section termination rsop cpu line generation tlop line termination rlop path generation tpop path trace buffer sptb path termination rpop packet/atm mapping tpp/tacp system layer interface posphy-3 packet interface / utopia-3 cell interface pif/uif packet/atm demapping rpp/racp renb rfclko rfclk rerr reop rmod[1..0] rdat[31..0] rprty rval rsop gpio[7..0] pmtick lcd-p berm jtag txrclk oe trstb tms tck tdi tdo transport overhead extraction roap rspclk1 rspvalid1 rspdat1 rspvalid2 rspdat2 rspclk2 rtohfp rtoh[3..0] rtohclk rtohvalid rspfp transport overhead insertion toap tspclk1 tspfp1 tspren1 rtohfp ttohen ttohclk ttohren tspdat1 tspclk2 tspfp2 tspren2 tspdat2 ttoh[3..0] tenb tfclko tfclk terr teop tmod[1..0] tdat[31..0] tprty dtpa tsop tlsyncttl tlsyncldvs+/- tloutser+/- tlclkser+/- cmu + mux cmurefclk+/- cmufilter+/- cmurefsel[1..0] cmulockdet looptiming rlinser+/- cru + dmx crurefclk+/- crufilter+/- crurefoutsel crulockdet crurefsel[1..0] phy crurecclk+/- cmurefdet rxts txst phy4bitsel lopc clkrsten dmx rlprty4+/- rlin4[3..0]+/- rlclk4+/- mux tlprty4+/- tlout[3..0]+/- tlclk4o+/- tlclk4+/- crurefdet rlinsermid figure 1.1. VSC9142 functional block diagram
g56054-0, rev 1.0 sonet/sdh 2.5gbps transport terminating transceiver VSC9142 . 4.0 electrical & mechanical data page 3 . 1.2 VSC9142 functional blocks
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6 bottom view die side 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 654321 a1 ball pad corner a b c d e f g h j k l m n p r t u v w y aa ab ac ad figure 1.4. VSC9142 320 bga ball pad identification
g56054-0, rev 1.0 sonet/sdh 2.5gbps transport terminating transceiver VSC9142 . 4.0 electrical & mechanical data page 19 . table 1.1. hardware signal definitions (1 of 12) pin label pad i/o type signal name description rlinser- rlinser+ f24 g24 i pecl serial line receive data serial line data input. rlin4[0]- rlin4[0]+ rlin4[1]- rlin4[1]+ rlin4[2]- rlin4[2]+ rlin4[3]- rlin4[3]+ d22 e21 e22 d23 f21 f22 e23 f23 i lvds parallel line receive data this is the parallel line-side receive data bus for the incoming sts-48c/stm-16 au-4-16c data stream. rlin4[3] is the most significant and first bit arriving bit on the serial data stream. rlin4[3..0] is sampled on the rising edge of rlclk4+. rlin4[3..0]+ are the true signal values. rlprty4- rlprty4+ c22 c23 i lvds parallel line receive parity this is a programmable (even/odd) parity bit for parallel line receive data rlin4[3..0]. rlprty4 is sampled on the rising edge of rlclk4+. rlprty4+ is the true signal value. rlclk4- rlclk4+ d24 c24 ilvds parallel line receive clock this is the reference clock input for the parallel line-receive data carried in rlin4[3..0]+/-. the nominal frequency is 622.08 mhz for sts-48c/stm-16 au-4-16c operation. rlclk4+ is the true signal value. rlinsermid h23 i n/a serial line receive data center tap rlinser+/- has a 100 ohms on-chip resistor termination which has a center tap between the two 50 ohm resistors. the center tap can be used to bias the centerpoint for single ended applications or decoupled to gnd for differential applications. crurefclk- crurefclk+ j21 j22 i pecl cru reference clock this input is the reference clock used within phase locked loop in the clock recovery unit. crurefdet ad15 o ttl cru reference clock detect this output indicates the presense of clock transistions on crurefclk+/-. the signal is active high. crulockdet ac15 o ttl cru lock detect this output indicatest the lock status of the pll within the cru with respect to crurefclk+/-. the signal is active high. crurefsel1 crurefsel0 ab15 aa15 ittl cru reference clock select these inputs select which frequency is to be expected on crurefclk+/-. the binary combination of the two pins are described below (crurefsel0 noted first). 00 78 mhz 01 155 mhz 10 311 mhz crurecclk- crurecclk+ k24 j24 o pecl cru recovered clock this reference clock output is derived from the 2.5 gb/s reference clock divided down according to crurefsel[1..0]. crufilter- crufilter+ l23 k22 i n/a cru loop filter these inputs are brought off-chip to connect to a capacitor which completes the cru loop filter. crufilter+ should be connected to one side of a 0.1uf capacitor while crufilter- should be connected to the other side of the capacitor. physical interface (phy) signals crurefoutsel ad16 i ttl crurecclk output selector this input selects the clock to be output on pins crurecclk+/-. a high level selects a looped version of the reference clock, while a low level selects the divided version of the recovered clock.
g56054, rev 1.0 sts-48c physical layer packet/atm over sonet/sdh device VSC9142 page 20 1.0 product description . table 1.1 hardware signal definitions (2 of 12) pin label pad i/o type signal name description tloutser- tloutser+ n24 m24 opecl serial line transmit data serial line data output. tlclkser- tlclkser+ r24 p24 o pecl serial line transmit clock serial line clock output tlout4[0]- tlout4[0]+ tlout4[1]- tlout4[1]+ tlout4[2]- tlout4[2]+ tlout4[3]- tlout4[3]+ v23 v22 v24 w23 y22 w21 aa24 aa23 o lvds parallel line transmit data this is the parallel line-side transmit data bus for the outgoing sts-48c/stm-16 au-4-16c data stream. tlout4[3] is the most significant and first transmitted bit in the serial data stream. tlout4[3..0] is latched out the rising edge of tlclk4+, but is centered about tlclk4o-. tlout[3..0]+ are the true signal values. tlprty4- tlprty4+ u23 u22 o lvds parallel line transmit parity this is a programmable (even/odd) parity bit for parallel line transmit data tlout4[3..0]. tlprty4 is latched out on the rising edge of tlclk4+, but is centered about tlclk4o-. tlprty4+ is the true signal value. tlclk4- tlclk4+ t24 u24 ilvds parallel line transmit clock this is the reference clock input for the parallel line-transmit data carried in tlout4[3..0]+/-. the nominal frequency is 622.08 mhz for sts-48c/stm-16 au-4-16c operation. tlclk4+ is the true signal value. tlclk4o- tlclk4o+ y24 w24 o lvds parallel line transmit clock out this output is the looped version of the reference clock input tlclk4+/-. the nominal frequency is 622.08 mhz for sts- 48c/stm-16 au-4-16c operation. tlclk4o+ is the true signal value. cmurefclk- cmurefclk+ n23 m23 ipecl cmu reference clock this input is the reference clock used for the clock multiplier unit. cmurefdet ac17 o ttl cmu reference clock detect this output indicates the presense of clock transistions on cmurefclk+/-. the signal is active high. cmulockdet ac16 o ttl cmu lock detect this output indicatest the lock status of the pll within the cmu with respect to cmurefclk+/-. the signal is active high. cmurefsel1 cmurefsel0 ab16 aa16 i ttl cmu reference clock select these inputs select which frequency is to be expected on cmurefclk+/-. the binary combination of the two pins are described below (cmurefsel0 noted first). 00 78 mhz 01 155 mhz 10 311 mhz physical interface (phy) signals (cont.) cmufilter- cmufilter+ l22 l21 i n/a cmu loop filter these inputs are brought off-chip to connect to a capacitor which completes the cmu loop filter. cmufilter+ should be connected to one side of a 0.1uf capacitor while cmufilter- should be connected to the other side of the capacitor.
g56054-0, rev 1.0 sonet/sdh 2.5gbps transport terminating transceiver VSC9142 . 4.0 electrical & mechanical data page 21 . table 1.1 hardware signal definitions (3 of 12) pin label pad i/o type signal name description clkrsten ac12 i ttl clock reset enable asserting clkrsten halts all primary clock outputs (txrclk, rxrclk, rspclk1, rspclk2, rtohclk, tspclk1, tspclk2, and ttohclk) during master reset. if deasserted, all primary clock outputs run normally during master reset. looptiming ad18 i ttl looptime enable this input enables looptiming which forces the cmu and subsequent tx clocks to be referenced to the recovered line clock. this signal is active high although the associated register can override the pin. lopc ac13 i ttl loss of optical carrier this input is used to monitor the optical carrier signal status, and detected changes which can be used to generate interrupts. this enables the optical signal to be monitored via the device cpu interface. when lopc is asserted, the receive processor is optionally clocked by the transmit clock (derived from tlclk4+/- or the cmu clock). phy4bitsel ab14 i ttl 4-bit physical interface select this input selects the 4 bit interface and disables the cru and cmu. this input is active high. tlsynclvds- tlsynclvds+ t22 t21 ilvdstransmit synchronization this is the lvds input for the synchronous reset signal for the line-side transmit processor. (note: tlsynclvds/ tlsyncttl is intended for use in sts-192/stm-64 applications only.) tlsyncttl ab23 i ttl transmit synchronization this is the ttl input for the synchronous reset signal for the line-side transmit processor. (note: tlsynclvds/ tlsyncttl is intended for use in sts-192/stm-64 applications only.) rxrclk ad12 o ttl receive reference clock this reference clock output is derived from the serial or parallel receive line clock and can be programmed to operate at 78mhz, 38mhz, 19mhz, or 8khz frequencies. physical interface (phy) signals (cont.) txrclk b21 o ttl line transmit reference clock this reference clock output is derived from the serial or parallel transmit line clock and can be programmed to operate at 78mhz, 38mhz, 19mhz, or 8khz frequencies.
g56054, rev 1.0 sts-48c physical layer packet/atm over sonet/sdh device VSC9142 page 22 1.0 product description . table 1.1 hardware signal definitions (4 of 12) pin label pad i/o type signal name description drop side (pif/uif) transmit signals tdat/tudata[0] tdat/tudata[1] tdat/tudata[2] tdat/tudata[3] tdat/tudata[4] tdat/tudata[5] tdat/tudata[6] tdat/tudata[7] tdat/tudata[8] tdat/tudata[9] tdat/tudata[10] tdat/tudata[11] tdat/tudata[12] tdat/tudata[13] tdat/tudata[14] tdat/tudata[15] tdat/tudata[16] tdat/tudata[17] tdat/tudata[18] tdat/tudata[19] tdat/tudata[20] tdat/tudata[21] tdat/tudata[22] tdat/tudata[23] tdat/tudata[24] tdat/tudata[25] tdat/tudata[26] tdat/tudata[27] tdat/tudata[28] tdat/tudata[29] tdat/tudata[30] tdat/tudata[31] j3 j4 h3 g1 g2 g3 f1 f2 f3 e2 e3 f4 d1 d2 d3 e4 c1 c2 d5 b3 a3 c4 b4 d6 c5 a4 c6 b5 b6 c7 a6 d9 ittl transmit packet data bus (tdat x ) or utopia transmit cell data bus (tudata x ) pos mode: this 32-bit data bus is used to drive four-octet true data from the packet to phy layer. tdat[31] is the msb. packets are aligned to the 32-bit tdat x boundary. atm mode: this 32-bit data bus is used to drive four-octet true data from the atm to phy layer. tudata[31] is the msb.
g56054-0, rev 1.0 sonet/sdh 2.5gbps transport terminating transceiver VSC9142 . 4.0 electrical & mechanical data page 23 . table 1.1 hardware signal definitions (5 of 12) pin label pad i/o type signal name description pos mode: tprty atm mode: tuprty c8 i ttl transmit bus parity pos mode: trprty is the odd/even (programmable, default odd) parity bit over tdat[31..0]. the signal is only valid when asserted simultaneously with tenb. atm mode: tuprty is the odd/even (programmable, default odd) parity bit over tudata[31..0], driven by the atm layer. the signal is valid when asserted simultaneously with tuenb*. pos mode: tmod[1] tmod[0] a7 b7 ittl transmit word modulo pos mode only: these inputs are used to qualify tdat x data octets. the state of tmod[1,0] defines which of the four tdat octets contain valid data when both teop and tenb are asserted. non-eop words always contain four valid tdat octets. pos mode: tsop atm mode: tusoc c9 i ttl transmit start of packet or utopia transmit start of cell pos mode: tsop is asserted (active high) by the packet layer to indicate that tdat x contains the first valid octet of a new packet. the signal is valid when asserted simultaneously with tenb. the packet interface can be operated without using this signal. atm mode: tusoc is asserted (active high) by the atm layer to indicate that tudata x contains the first valid octet of the cell. the signal is only valid when asserted simultaneously with tuenb*. pos mode: teop d10 i ttl transmit end of packet pos mode only: teop is asserted (active high) by the packet layer to indicate that tdat x contains the last valid octet of the packet. only valid when asserted simultaneously with tenb. pos mode: dtpa atm mode: tufull*/ tuclav a9 o ttl transmit polled- phy packet available or transmit full/cell available pos mode: dtpa transitions high when a programmable minimum number of octets are available in the tx fifo. once high, the dtpa indicates that the tx fifo is not full. when dtpa transitions low, it optionally indicates that the tx fifo is full or near full. atm mode: tufull*/tuclav is indicates ?full? or ?cell available? status of utopia transmit interface for flow control. tufull* is for word-level flow control; tuclav is for cell-level flow control. polarity is selectable via an internal register bit (i.e., tufull* active low/tuclav active high, or vice versa). pos mode: terr b9 i ttl transmit error indicator pos mode only: an active terr flag can be used to force hdlc frame abortion, or insertion of fcs error in the transmitted hdlc/ppp frames. the terr value is only valid for teop-marked words, and is ignored for all other word writes. pos mode: tenb atm mode: tuenb* c10 i ttl transmit write enable pos mode: tenb is used by the packet layer to indicate cycles w hen tdat x contains valid packet data (active low). atm mode: tuenb* is used by the atm layer to indicate cycles w hen tudata x contains valid cell data (active low). pos mode: tfclk atm mode: tuclk a10 i ttl transmit write clock pos mode: tfclk is a reference clock provided by the packet layer to the phy layer to synchronize transfers on tdat x . atm mode: tuclk is a reference clock provided by the atm layer to the phy layer to synchronize transfers on tudata x . drop side (pif/uif) transmit signals (cont.) pos mode: tfclko atm mode: tuclko b10 o ttl transmit write clock looped pos mode: tfclko is the tfclk transfer synchronization reference clock from the packet layer looped out. atm mode: tuclko is the tuclk transfer synchronization reference clock from the atm layer looped out.
g56054, rev 1.0 sts-48c physical layer packet/atm over sonet/sdh device VSC9142 page 24 1.0 product description . table 1.1 hardware signal definitions (6 of 12) pin label pad i/o type signal name description rdat/rudata[0] rdat/rudata[1] rdat/rudata[2] rdat/rudata[3] rdat/rudata[4] rdat/rudata[5] rdat/rudata[6] rdat/rudata[7] rdat/rudata[8] rdat/rudata[9] rdat/rudata[10] rdat/rudata[11] rdat/rudata[12] rdat/rudata[13] rdat/rudata[14] rdat/rudata[15] rdat/rudata[16] rdat/rudata[17] rdat/rudata[18] rdat/rudata[19] rdat/rudata[20] rdat/rudata[21] rdat/rudata[22] rdat/rudata[23] rdat/rudata[24] rdat/rudata[25] rdat/rudata[26] rdat/rudata[27] rdat/rudata[28] rdat/rudata[29] rdat/rudata[30] rdat/rudata[31] w1 v3 v2 v1 u3 u2 t4 t3 t2 t1 r4 r3 r2 r1 p3 p2 n1 n4 n3 n2 m3 m4 m2 m1 l2 l3 k1 k2 k3 k4 j1 j2 ottl recevie packet data bus (rdat x ) or receive cell data bus (rudata x ) pos mode: this 32-bit data bus is used to drive four-octet true data from the phy to packet layer. rdat[31] is the msb. packets are aligned to the 32-bit rdat x boundary. atm mode: this 32-bit data bus is used to drive four-octet true data from the phy to atm layer. rudata[31] is the msb. pos mode: rprty atm mode: ruprty y3 o ttl receive bus parity pos mode: rprty is the odd/even (programmable, default odd) parity bit over rdat[31..0]. atm mode: ruprty is the odd/even (programmable, default odd) parity bit over rudata[31..0]. pos mode: rmod[1] rmod[0] w2 w3 ottlreceive word modulo pos mode only: these outputs are used to qualify rdat x data octets. the state of rmod[1,0] defines which of the four rdat octets contain valid data when reop is asserted. non- eop words always contain four valid rdat octets. drop side (pif/uif) receive signals pos mode: rsop atm mode: rusoc aa1 o ttl receive start of packet or utopia receive start of cell pos mode: rsop is asserted (active high) by the packet layer to indicate that rdat x contains the first valid octet of a new packet. the packet interface can be operated without using this signal. atm mode: rusoc is asserted (active high) by the atm layer to indicate that rudata x contains the first valid octet of a cell. this signal is used to support multiple phy configurations.
g56054-0, rev 1.0 sonet/sdh 2.5gbps transport terminating transceiver VSC9142 . 4.0 electrical & mechanical data page 25 . table 1.1 hardware signal definitions (7 of 12) pin label pad i/o type signal name description pos mode: reop ab2 o ttl receive end of packet pos mode only: reop is asserted (active high) to indicate that rdat x contains the last valid octet of the packet. pos mode: rval atm mode: ruempty*/ ruclav aa2 o ttl receive data valid or receive empty/cell available pos mode: rval asserted (active high) indicates that the recevie data signals (rdat x , rsop, reop, rmod, rprty, and rerr) are valid. when ral is low, all receive signals are invalid and must be disregarded. rval transitions low when the rx fifo is empty or the end of a packet is reached, and data will not be removed from the rx fifo while rval is low. once deasserted, rval remains so until the current phy has been deselected. atm mode: ruempty*/ruclav indicates ? empty ? or ? cell available ? status of the utopia receive interface for flow control. ruempty* is for word-level flow control; ruclav is for cell- level flow control. polarity is selectable via an internal register bit (i.e., ruclav active high/ruempty* active low, or vice versa). pos mode: rerr w4 o ttl receive error indicator pos mode only: an asserted rerr flag (active high) indicates that the packet contained an error (i.e., abort/fcs error). the rerr flag is only asserted during eop-marked words. pos mode: renb atm mode: ruenb* aa3 i ttl receive read enable pos mode: renb is used by the packet layer to indicate that the rval, rsop, rprty, rdat x , rmod x , reop, and rerr signals will be sampled at the end of the nest cycle (active low). atm mode: ruenb* is used by the atm layer to indicate that rudata, rusoc, and rprty will be sampled at the end of the nest cycle (active low). pos mode: rfclk atm mode: ruclk y4 i ttl receive fifo write clock or receive write clock pos mode: rfclk is a reference clock provided by the packet layer to the phy layer to synchronize transfers on rdat x . atm mode: ruclk is a reference clock provided by the atm layer to the phy layer to synchronize transfers on rudata x . drop side (pif/uif) receive signals (cont.) pos mode: rfclko atm mode: ruclko aa4 o ttl receive fifo write clock looped or receive write clock looped pos mode: rfclko is the rfclk transfer synchronization reference clock looped out. atm mode: ruclko is the ruclk transfer synchronization reference clock looped out. txts aa6 o ttl transmit time stamp txts is an active high pulse generated when a cell/packet exits the tpp block. the difference in time between a txts pulse and a tsop/tusoc pulse can be used to determine transmit fifo latency. time stamp signals rxts ac3 o ttl receive time stamp rxts is an active high pulse generated when a new cell/packet arrives in the rpp block. the difference in time between an rxts pulse and an rsop/rusoc pulse is used to determine receive fifo latency. los ab5 o ttl loss of signal this is a status signal for loss of signal (los) detection (active high). los status is also indicated by an internal register bit. lof aa13 o ttl loss of frame this is a status signal for loss of frame (lof) detection (active high). lof status is also indicated by an internal register bit. rx alarm signals lcd-p ab4 o ttl loss of cell delineation this signal is asserted when the cell delineation state machine is not in sync state. this alarm indication is also available via internal register access.
g56054, rev 1.0 sts-48c physical layer packet/atm over sonet/sdh device VSC9142 page 26 1.0 product description . table 1.1 hardware signal definitions (8 of 12) pin label pad i/o type signal name description rspfp c18 o ttl receive special purpose frame pulse this is a frame reference for special purpose serial output ports rspdat x . rspfp outputs a single clock-cycle-wide pulse coincident with the first bit on the serial data streams. active high, rspfp transitions occur on falling edges of rspclk x . x =[1,2] rspclk1 a19 ottl receive special purpose clock 1 this is a clock reference for rspdat1 on special purpose serial output port 1. the frequency is 2.16mhz with a 50% duty cycle (optionally gapped to match the bandwidth of rspdat1). rspdat1 d20 o ttl receive special purpose data 1 this is the data output for receive special purpose serial port 1. rspdat1 transitions occur on the falling edge of rspclk1. rspvalid1 c20 o ttl receive special purpose valid 1 this is a status signal for receive transport overhead port 1. rspvalid1 is asserted when valid data is present on rspdat1 (programmable active state). transitions occur on rspclk1 falling edges. rspclk2 b18 o ttl receive special purpose clock 2 this is a clock reference for rspdat2 on special purpose serial output port 2. the frequency is 2.16mhz with a 50% duty cycle (optionally gapped to match the bandwidth of rspdat2). rspdat2 c17 o ttl receive special purpose data 2 this is the data output for receive special purpose serial port 2. rspdat2 transitions occur on the falling edge of rspclk2. rspvalid2 b17 o ttl receive special purpose valid 2 this is a status signal for receive transport overhead port 2. rspvalid2 is asserted when valid data is present on rspdat2 (programmable active state). transitions occur on rspclk2 falling edges. rtohclk b16 o ttl receive transport overhead clock this is a clock reference for rtoh[3..0] on the receive transport overhead port. the frequency is 38.88mhz (50% duty cycle). rtohvalid b19 o ttl receive transport overhead valid this is the valid status signal for the receive transport overhead port. rtohvalid is asserted when valid data is present on rtoh[3..0] (programmable active state). rtohvalid changes on the falling edge of rtohclk. rtohfp a18 o ttl receive transport overhead frame pulse this is a frame reference for the receive transport overhead port. rtohfp outputs a single-cycle-wide pulse coincident with the first bit(s) of the first a1 octet output on rtoh[3..0]. rtohfp transitions occur on the falling edge of rtohclk. rx overhead transport access processor (roap) signals rtoh[0] rtoh[1] rtoh[2] rtoh[3] a21 d19 b20 c19 o ttl receive transport overhead data these are the data outputs for the receive transport overhead (section and line) octets extracted from the incoming sts-48 data stream. rtoh[3..0] carries the entire transport ovehead in the order the octets are received. the most significant nibble (first received) is output first. rtoh[3] is the most significant bit. rtoh[3..0] transitions occur on the falling edge of rtohclk.
g56054-0, rev 1.0 sonet/sdh 2.5gbps transport terminating transceiver VSC9142 . 4.0 electrical & mechanical data page 27 . table 1.1 hardware signal definitions (9 of 12) pin label pad i/o type signal name description tspclk1 a16 o ttl transmit special purpose clock 1 this is a clock reference for transmit special purpose port 1. the frequency is 2.16mhz with a 50% duty cycle (opti onally gapped to match the bandwidth of tspdat1). tspfp1 a13 o ttl transmit special purpose frame pulse 1 this is a frame reference for transmit special purpose port 1. mode 1 (tspclk1 continuous): tspfp1 outputs a single-cycle- wide pulse indicating the start of a new data stream on tspdat1. after tspfp1 is asserted, the first bit of tspdat1 is sampled on the second rising edge of tspclk1. tspfp1 transitions occur on the falling edge of tspclk1. mode 2 (tspclk1 gapped): tspfp1 outputs a single-cycle- wide pulse (variable width due to the gapped clock) indicating the start of a new data stream on tspdat1. after tspfp1 is asserted, the first bit of tspdat1 is sampled on the second rising edge of tspclk1. tspfp1 transitions occur on the falling edge of tspclk1. tspren1 b15 o ttl transmit special purpose read enable 1 this is a read enable for transmit special purpose port 1. tspren1 assertion to tspdat1 sampling is programmable. tspren1 transitions occur on tspclk1 falling edges. tspdat1 a15 i ttl transmit special purpose data 1 this is the serial data input for transmit special purpose port 1. tspdat1 is sampled on the rising edge of tspclk1. tspclk2 b13 o ttl transmit special purpose clock 2 this is a clock reference for transmit special purpose port 2. the frequency is 2.16mhz with a 50% duty cycle (opti onally gapped to match the bandwidth of tspdat2). tspfp2 b12 o ttl transmit special purpose frame pulse 2 this is a frame reference for transmit special purpose port 2. mode 1 (tspclk2 continuous): tspfp2 outputs a single-cycle- wide pulse indicating the start of a new data stream on tspdat2. after tspfp2 is asserted, the first bit of tspdat2 is sampled on the second rising edge of tspclk2. tspfp2 transitions occur on the falling edge of tspclk2. mode 2 (tspclk2 gapped): tspfp2 outputs a single-cycle- wide pulse (variable width due to the gapped clock) indicating the start of a new data stream on tspdat2. after tspfp2 is asserted, the first bit of tspdat2 is sampled on the second rising edge of tspclk2. tspfp2 transitions occur on the falling edge of tspclk2. tspren2 b11 o ttl transmit special purpose read enable 2 this is a read enable for transmit special purpose port 2. tspren2 assertion to tspdat2 sampling is programmable. tspren2 transitions occur on tspclk2 falling edges. tspdat2 d13 i ttl transmit special purpose data 2 this is the serial data input for transmit special purpose port 2. tspdat2 is sampled on the rising edge of tspclk2. ttohclk c13 o ttl transmit transport overhead clock this is a clock reference for the transmit transport overhead port. the frequency is 38.88mhz with a 50% duty cycle. ttohfp c12 o ttl transmit transport overhead frame pulse this is a frame reference for the transmit transport overhead port. ttohfp outputs a single clock-cycle-wide pulse indicating the start of a new data stream on ttoh[3..0]. the time from ttohfp assertion to sampling the first bit on ttoh[3..0] is programmable (see ttohren). ttohfp transitions on a falling edge of ttohclk. tx overhead transport access processor (toap) signals ttohren a12 o ttl transmit transport overhead read enable this is a read enable for ttoh[3..0]. the time from ttohren assertion to ttoh[3..0] sampling is programmable. ttohren transitions occur on the falling edge of ttohclk.
g56054, rev 1.0 sts-48c physical layer packet/atm over sonet/sdh device VSC9142 page 28 1.0 product description . table 1.1 hardware signal definitions (10 of 12) pin label pad i/o type signal name description ttohen c14 i ttl transmit transport overhead enable when asserted, this signal enables insertion of ttoh[3..0] in the corresponding transport overhead octet of the outgoing sts-48 data stream. transport overhead for the entire sts-48 is input as 4-bit nibbles on ttoh[3..0] (see ttoh[3..0] description). ttohen assertion during the first nibble of an overhead octet enables the corresponding overhead octet on ttoh[3..0]. note: the section and line transmit overhead processing blocks (tsop/tlop) can selectively overwrite overhead octets inserted through the ttoh interface. tx overhead transport access processor (toap) signals ttoh[0] ttoh[1] ttoh[2] ttoh[3] d16 c16 d15 c15 i ttl transmit transport overhead data these are the data inputs for the transmit transport overhead (section and line) octets to be inserted in the outgoing sts-48 data stream. ttoh[3..0] carries the entire transport overhead in the order the octets are to be inserted. the most significant nibble (first received) is input first. ttoh[3] is the most significant bit. ttoh[3..0] is sampled on the rising edge of ttohclk. d[0] d[1] d[2] d[3] d[4] d[5] d[6] d[7] ab6 ac4 ad4 ab7 ac5 ac6 ad6 ac7 i/o ttl cpu data this is a bidirectional data bus that provides microcontroller read/write access for transferring data to and from the device ? s internal registers. microprocessor interface signals a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] a[8] ab9 ad7 aa10 ac9 ad9 ac10 ab11 ac11 ab13 ittl cpu address this is the register address bus used to select specific internal registers during microcontroller read/write accesses.
g56054-0, rev 1.0 sonet/sdh 2.5gbps transport terminating transceiver VSC9142 . 4.0 electrical & mechanical data page 29 . table 1.1 hardware signal definitions (11 of 12) pin label pad i/o type signal name description ale aa12 ittl cpu address latch enable this signal is used to latch internal address bus signals, enabling access to the device ? s multiplexed address/data bus. when low the address bus a[8..0] is latched internally. when high the internal address bus latches are transparent, which enables the bus to interface with multiplexed address/data. the ale signal has an internal pull-up resistor. csb ad10 i ttl cpu chip select (active low) this signal must be asserted to enable internal register read/write access cycles (active low). the csb signal is used in conjunction with the rdb/wrb signals. the csb signal has an internal pull- up resistor. rdb ab8 i ttl cpu read enable (active low) this signal is used for internal register read operations. when rdb and csb are both asserted (active low), data in the register selected by a[8..0] is presented at d[7..0]. the rdb signal has an internal pull-up resistor. wrb ab10 i ttl cpu write enable (active low) this signal is used for internal register write operations. when wrb and csb are both asserted (active low), data present at d[7..0] is written to the register selected by a[8..0]. the wrb signal has an internal pull-up resistor. intb aa9 o ttl cpu interrupt (active low) this signal is asserted (active low) when an internal interrupt source is pending and the interrupt is unmasked (enabled). the intb signal is de-asserted when the interrupt pending bits have been cleared. the intb is an open-drain signal. rstb ad3 i ttl chip reset (active low) this signal is used to perform an asynchronous reset of the device (active low). the device is held in a reset state while the rstb signal is low. the signal is schmitt-trigged with an internal pull-up resistor. all outputs are tristated when rstb is asserted. pmtick ab12 i/o ttl performance monitoring tick this bidirectional signal pin provides a means of monitoring pm ticks (performance monitoring ticks) and latching internal performance monitoring counters. output: when configured as an output, this signal is optionally asserted when the internal pmtick timer generates a ? pm tick ? , which latches the performance monitoring counters in the device. input: a low-to-high transition optionally latches the performance monitoring counters in the device. note: this pin is configured as an input on reset. microprocessor (cpu) interface signals gpio[0] gpio[1] gpio[2] gpio[3] gpio[4] gpio[5] gpio[6] gpio[7] aa20 ab20 aa19 ac20 ab19 ac19 ad19 ab18 i/o ttl general purpose input/output these are general purpose pins that are individually-configurable as inputs or outputs. they are intended for user-customizable control and monitoring functions between the VSC9142 and external devices.
g56054, rev 1.0 sts-48c physical layer packet/atm over sonet/sdh device VSC9142 page 30 1.0 product description . table 1.1 hardware signal definitions (12 of 12) pin label pad i/o type signal name description tdo ac21 o ttl jtag test data output this signal carries test data out of the device via the ieee p1149.1 test access port. tdo is updated on the falling edge of tck. the tdo signal is a tristate output that is inactive except when data scan shifting is in progress. tdi ad22 i ttl jtag test data input the signal carries test data into the device via the ieee p1149.1 test access port. tdi is sampled on the rising edge of tck. tdi has an internal pull-up resistor. tck ab21 i ttl jtag test clock this signal provides timing for test operations that are carried out using the ieee p1149.1 test access port. tms ac22 i ttl jtag test mode select this signal controls the test operations that are carried out using the ieee p1149.1 test access port. tms is sampled on the rising edge of tck. tms has an internal pull-up resistor. trstb ab24 i ttl jtag test reset this signal is an asynchronous reset for the ieee p1149.1 test access port (active low). trstb is a schmitt-triggered input with an internal pull-up resistor. jtag test access port signals oe ad21 i ttl chip output enable this signal is the test access port enable (active high). when deasserted (low), all ttl device outputs are tristated. oe has an internal pull-up resistor. notice vitesse semiconductor corporation (?vitesse?) provides this document for informational purposes only. this document contains pr e-production information about vitesse products in their concept, development and/or testing phase. all information in this document, including descript ions of features, functions, performance, technical specifications and availability, is subject to change without notice at any time. nothing contained in t his document shall be construed as extending any warranty or promise, express or implied, that any vitesse product will be available as described or will be suita ble for or will accomplish any particular task. vitesse products are not intended for use in life support appliances, devices or systems. use of a vitesse product in such appl ications without written consent is prohibited. corporate headquarters vitesse semiconductor corporation ? 741 calle plano ? camarillo, ca 93012 tel: 1-800-vitesse ? fax: (805) 987-5896 ? email: prodinfo@vitesse.com www.vitesse.com this document is an excerpt of the VSC9142 data book. for the complete data book, please contact your local sales representativ e (nda required).

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